The AMD EPYC initially manifests as a 32-core, system-on-a-chip (SoC) design with two high-performance threads per core. It supports eight DDR4 memory channels per SoC – in a dual processor configuration that is 32 DIMMS and up to four terabytes of memory.
Matthew Eastwood, senior vice-president, IDC research, said, “Today’s single-socket server offerings push buyers toward purchasing a more expensive two-socket server just to get the memory bandwidth and I/O they need to support the compute performance of the cores.
“There are no fully-featured, high-performance server processors available today in a single-socket configuration. EPYC changes that dynamic by offering a single-processor solution that delivers the right-sized number of high-performance cores, memory, and I/O for today’s workloads.”
Asian research company Trendforce says more than half of global server demand will come from data centres by 2020 and Intel will be the long-term leader of server processors. It says that while AMD has transitioned to the more cutting-edge manufacturing technologies, it will not be able to expand market share significantly in the short term.
Trendforce says that AMD’s EPYC (formerly codenamed Naples) has a chance to break into the mid-range segment of the server processor market. AMD’s EPYC processors are made using the 14nm process and represent a huge leap from the company’s earlier Opteron solutions that came from the 32nm and the 28nm processes.
It said that, showing a large increase in computing power, the EPYC platform would allow AMD to challenge Intel in the mid-range market by directly competing against that latter’s solutions such as Xeon E5 v4 2600. The competitive advantage of the Naples platform was noticeable in the mid-range market, especially in terms of having lower average selling prices for its solutions, Trendforce added.
Intel’s latest Purley platform Xeon E7 v5 series is built using the 14nm process. It is designed for high-performance servers, featuring solutions with 8 sockets, and ISA and C602 chipsets that allow scalable buffer memory to further improve computing capability.