HP beats Moore's Law with new chip architecture

Stan Beer
Wednesday, 17 January 2007 02:17

Your IT - Home IT

A new type of nano-scale architecture developed in the research labs of Hewlett-Packard could beat Moore's Law and advance the progress of of microprocessor development three generations in one hit. The new architecture uses a design technique that will enable chip makers to pack eight times as many transistors as is currently possible on a standard 45nm field programmable gate array (FPGA) chip.

Currently, conventional FPGA chips use between 80 and 90% of their CMOS silicon for signal routing wires, leaving a relatively small amount for logic processing transistors. However, researchers Greg Snider and Stan Williams of HP Labs have developed a way to remove the signal routing wires from the silicon, leaving more room for logic processing transistors.

The new technique uses an architecture called “field programmable nanowire interconnect (FPNI)” which replaces the current signal routing with a crossbar made up of super thin 15nm wires which sits on a layer above the silicon-based transistors to route the signals.

The researchers, who have constructed tests using 17nm wires, say that using a cross bar with 15nm wires on FPNI architecture would enable eight times as many transistors to be housed on a 45nm chip without needing to shrink the size of the transistors.

“The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances,” said Snider, senior architect, Quantum Science Research, HP Labs. “We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.”

What's more, the new architecture would use less power than chips today, say the researchers.

According to the researchers, by 2020 using 4.5nm wires it should be possible to pack in the same amount of transistors in a space of just 4% of what is currently possible on a 45nm chip.