HP rearranges furniture to pack more on chips

Stan Beer
Tuesday, 16 January 2007 17:09

Your IT - Home IT

Hewlett-Packard has come up with a way to pack eight times as many transistors as is currently possible on a single 45nm chip using a new nanotechnology based architecture. The new architecture has the potential of instantly leapfrogging processor power across three generations of Moore's Law, which states that the number of transistors on a chip will double every 24 months.

Currently, conventional chips use between 80 and 90% of the silicon for signal routing wires, leaving a relatively small amount for logic processing transistors.

The research, by Greg Snider and Stan Williams of HP Labs, involves using an architecture called “field programmable nanowire interconnect (FPNI)” which enables much more of the silicon substrate to house logic processing transistors. This is achieved by removing the signal routing wires from the substrate and using a crossbar made up of 15nm wires which sits above the transistors to route the signals.

“The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances,” said Snider, senior architect, Quantum Science Research, HP Labs. “We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.”

According to the researchers, by 2020 using 4.5nm wires it should be possible to pack in the same amount of transistors in a space of just 4% of what is currently possible on a 45nm chip.