Intel gives details of Tera-Scale chip at forum

Stan Beer
Wednesday, 27 September 2006 18:30

Your IT - Home IT

Chipmaker Intel gave details yesterday of an experimental 80-core processor chip capable of suoercomputing performance measured in teraFLOPS.

• Announcements

In a speech at the Intel Developer Forum in San Francisco, Intel Senior Fellow and Chief Technology Officer Justin Rattner outlined details of the chip.

Rattner outlined the importance of three major silicon breakthroughs. He started by revealing the first details of Intel’s programmable TeraFLOP processor. Containing 80 simple cores and operating at 3.1 GHz, the goal of the experimental chip is to test interconnect strategies for rapidly moving terabytes of data from core to core and between cores and memory.

“When combined with our recent breakthroughs in silicon photonics, these experimental chips address the three major requirements for tera-scale computing – teraFLOPS of performance, terabytes-per-second of memory bandwidth, and terabits-per-second of I/O capacity,” said Rattner. “While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers.”

Unlike existing chip designs where hundreds of millions of transistors are uniquely arranged, this chip’s design consists of 80 tiles laid out in an 8x10 block array. Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but is not Intel Architecture compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory.

The second major innovation is a 20 megabyte SRAM memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores.