War of words between AMD and Intel techs over shared cache

Stan Beer
Friday, 07 July 2006 12:30

Your IT - Home IT

As news filters through of chip maker AMD's falling sales for the second quarter, a war of words has erupted between senior technologists at AMD and market leader Intel about the effectiveness of Intel's new dual core processor technology.

Intel's Australian technical manager Graham Tucker has disputeded negative claims previously made by Michael Apthorpe, senior technical manager for AMD in Australia and New Zealand about Intel's new dual core Xeon Processsor 5100 series. In a previous interview, Apthorpe told iTWire that the dual core processor design which involves both cores sharing a single memory cache has both performance and power consumption disadvantages.

"There are two types of cache with processors and they are known as exclusive and inclusive cache," said Apthorpe. "With inclusive cache, you have one allocation of RAM. What happens is that if you're running a program and all of sudden you change programs, you have to stop and flush the entire cache and reallocate and reload it. That takes clock cycles to do and that's our competitor's product."

However, Apthorpe's counterpart at Intel, Graham Tucker, claims that not only is Apthorpe's statement about shared cache incorrect but in fact the exact opposite is true.

According to Tucker, shared cache actually has distinct performance advantages over discrete cache dual core processor systems, which is why the Xeon Processor 5100 series is beating its AMD Opteron competitor in performance benchmark tests.

"This is because applications typically may load up one core more than the other," he says.

"If that's the case, then one core may want a larger amount of cache than the other core. For example, in a Windows environment, say you were running a single threaded application. You would be loading up one core and for that core you would want to dynamically allocate more cache memory because that's the predominant application running. With shared cache, you have the ability to use the full 4 megabytes of the cache instead of being isolated to half of that as is the case with the Pentium D and AMD K8 architecture.

"We started with discrete caches on Pentium D," says Tucker. "The reason why we didn't implement shared cache then was because it was difficult. If you look at what AMD is doing for the future, they are planning a shared cache; it's in their roadmap. The reason it's difficult to implement is because there's a lot of logic you need to put in to make sure you're not degrading performance and to handle the synchronisation between the different cores."

Tucker says statements made by Apthorpe about the requirement to flush cache and reload it are incorrect.

"I dispute that because no flushing of the cache is necessary," he says. "Cache lines get overwritten as they become not so popular. They work on a statistical basis of the most frequently used instructions and data. I think the example Michael used was switching between applications. He suggested that the whole cache needed to be reflushed and in fact it doesn't."

Tucker also disputes statements by Apthorpe that shared cache is more power hungry than discrete cache.

"We actually use less power because of the smart cache design," he says. "We only turn on the segments of the cache that are being accessed. We've segmented the whole 4 megabytes of cache and effectively the cache that isn't used is powered down. Whereas in the (AMD) K8 architecture, everytime you access the discrete cache, the whole cache fires up. Even though the caches are smaller on K8, you have all the transistors alight. We use that same technique for other parts of the circuitry (on Xeon Processor 5100) and that's why with the core architecture we've gained a real power advantage."

According to Tucker, share cache is the technology architecure that all the major semiconductor manufacturers will use going forward.

"If you read any of the microprocessor forums about the way dual core and multi core is implemented, IBM has done this as well and we've done it on the Itanium architecture. It is just more difficult to implement, but if you ask AMD about their future plans, they'll share the same desire."

In recent quarters, AMD has made significant gains in marketshare over its larger rival with processors that had superior performance. The latest quarter indicates that AMD's march forward has come to a halt for the moment. Now that Intel has cut prices and appears to have leap-frogged its competitor in the performance stakes, is the party over for AMD or is it simply time out for a breather?