IBM, Hitachi team to shrink semiconductors

Stephen Withers
Tuesday, 11 March 2008 01:12

Your IT - Home IT

A two-year research agreement between IBM and Hitachi is aimed at further reducing the size of semiconductors.

Current chips are as fine as 45nm, but the two companies are aiming to produce 32 and 22nm devices.

The partners will be looking for ways to to improve the characterisation and measurement of transistor variation.

"Hitachi's cutting-edge semiconductor characterisation capabilities, and IBM's state-of-the-art CMOS research capabilities can help the two companies accelerate the pace of semiconductor innovation for the 32-nanometer generation and beyond," said Bernie Meyerson, vice president strategic alliances and CTO for IBM's systems and technology group. "By combining individual research strength and intellectual property we reduce the significant costs associated with research needed to advance the next generation of chip technology."

"Hitachi's significant expertise in analytical instrumentation and semiconductor physics can promote industry-leading research for next generation semiconductor technology," said Eiji Takeda, vice president, executive officer, and general manager of Hitachi's research and development group. "Our two companies have a long history of successful business collaboration and we look forward to extending this to include the semiconductor metrology research arena."

The work will be carried out at IBM's Thomas J Watson Research Center in Yorktown Heights and at the College of Nanoscale Science and Engineering's Albany NanoTech Complex.