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Information Technology News HP rearranges furniture to pack more on chips
Information Technology News HP rearranges furniture to pack more on chips | HP rearranges furniture to pack more on chips |
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| by Stan Beer | |
| Tuesday, 16 January 2007 | |
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The research, by Greg Snider and Stan Williams of HP Labs, involves using an architecture called “field programmable nanowire interconnect (FPNI)” which enables much more of the silicon substrate to house logic processing transistors. This is achieved by removing the signal routing wires from the substrate and using a crossbar made up of 15nm wires which sits above the transistors to route the signals. “The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances,” said Snider, senior architect, Quantum Science Research, HP Labs. “We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.” According to the researchers, by 2020 using 4.5nm wires it should be possible to pack in the same amount of transistors in a space of just 4% of what is currently possible on a 45nm chip.{moscomment}
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