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Information Technology News AMD extends x86 instruction set with SSE5
Information Technology News AMD extends x86 instruction set with SSE5 | AMD extends x86 instruction set with SSE5 |
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| by Stephen Withers | |
| Friday, 31 August 2007 | |
  
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"We are working closely with AMD to enable developers to quickly and easily leverage the SSE5 instruction set to enhance high performance computing, and the multi-core and multi-media capability of their software applications," said Douglas Miles, director of software tools company The Portland Group. "The impact of our designs are best realized when AMD-based servers, PCs and devices enable software to more effectively solve every-day problems and enhance every-day experiences," said Phil Hester, AMD's senior vice president and chief technology officer. "By announcing our plans to add SSE5 instructions to the x86 instruction set - and by making the specification available today - we are enabling open and collaborative software innovation that will bring AMD's advancements to life for our customers and end-users. SSE5 includes 46 new instructions that are intended to improve performance by increasing the work done per instructions and by reducing the need to save and reload register operands. This is achieved through the introduction of three- and four-operand instructions as opposed to the two-operand maximum of the current x86 architecture. For example, a single instruction can multiply two values and add the result to a third, making it easier to calculate the sum of the products of a list of paired numbers. This has applications in graphics, audio and other applications. SSE5 also introduces a new 16-bit floating-point data type that may be related to AMD's 'Fusion' plan to deliver a single component combining CPU and GPU functionality. |
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